Pulse Width Insensitive Design and Verification Methods

Shankar, Ruchi and Eswaran, Shalini and Bhat, Sharavathi and Balasubramanian, Lakshmanan (2020) Pulse Width Insensitive Design and Verification Methods. EAI Endorsed Transactions on Cloud Systems, 6 (17): e3. ISSN 2410-6895

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Abstract

Many embedded controllers have some critical system states that depend on an asynchronous event. Currently handling them in design depends on the availability of always-on slow clocks. In this paper we present a generic asynchronous design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenarios sensitive to exact arrival times of asynchronous events. This is enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality. These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitive applications.

Item Type: Article
Uncontrolled Keywords: Pulse-width sensitivity, glitch, glitch filter, GLS, SDF, AMS co-simulation, DMS co-simulation, Analog mixed-signal, Digital mixed-signal
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
QA75 Electronic computers. Computer science
Depositing User: EAI Editor II.
Date Deposited: 10 Sep 2020 07:31
Last Modified: 10 Sep 2020 07:31
URI: https://eprints.eudl.eu/id/eprint/142

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