Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications

Pham-Quoc, Cuong (2020) Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications. EAI Endorsed Transactions on Context-aware Systems and Applications, 7 (20): e5. ISSN 2409-0026

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Abstract

We present a case study of automatic FPGA-based hardware accelerator design using our proposed framework with the image processing domain. With the framework, the ultimate systems are optimized in both performance and energy consumption. Moreover, using the framework, designers can implement FPGA platforms without manually describing any hardware cores or the interconnect. The systems offer accelerations in execution time compared to traditional general purpose processors and accelerator systems designed manually. We use two applications in the image processing domain as experiments to report our work. Those are Canny edge detection and jpeg converter. The experiments are conducted in both embedded and high-performance computing platforms. Results show that we achieve overall speed-ups by up to 3.15´ and 2.87´ when compared to baseline systems in embedded and high-performance platforms, respectively. Our systems consume less energy than other FPGA-based systems by up to 66.5%.

Item Type: Article
Uncontrolled Keywords: FPGA-based design framework, Hardware accelerator, Image processing
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
QA75 Electronic computers. Computer science
Depositing User: EAI Editor II.
Date Deposited: 14 Sep 2020 11:16
Last Modified: 14 Sep 2020 11:16
URI: https://eprints.eudl.eu/id/eprint/278

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