Implementation of NoC on FPGA with Area and Power Optimization

Ijaz, Momil and Urooj, Huma and Sethi, Muhammad Athar Javed (2019) Implementation of NoC on FPGA with Area and Power Optimization. EAI Endorsed Transactions on Context-aware Systems and Applications, 6 (16): e5. ISSN 2409-0026

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Abstract

On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems, size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.

Item Type: Article
Uncontrolled Keywords: Network on chip, node, switching, packet, crossbar
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
QA75 Electronic computers. Computer science
Depositing User: EAI Editor II.
Date Deposited: 16 Sep 2020 08:24
Last Modified: 16 Sep 2020 08:24
URI: https://eprints.eudl.eu/id/eprint/298

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