Ranganayakulu, Dr.A. and Narayana, Dr.V. Surya and Rao, Dr.M.V. Nageswara (2021) Design of SOC Based SRAM Cluster for Reliability and Functional Safety Applications. In: I3CAC 2021, 7-8 June 2021, Bharath University, Chennai, India.
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Abstract
In this paper the design of SOC based SRAM cluster is implemented for reliability and functional safety. The main objective of this research is to improve the accuracy and reduce the delay using SOC based design. The designed system initially generates the network using network generator. This network generator basically uses the strategies of both user’s clusterization and hierarchy optimization. After the strategy of hierarchy structure the electronic design automation (EDA) generator will generate the test standards based on the access of tests. This generated components test will be extracted based on the standards. Next H-Array generator will generate the arrays of H-arrays for different cluster level sub networks. All these arrays will be cross compiled by mapping the cells. At last this will be saved in SRAM cluster. Hence the SOC based SRAM cluster will improve the accuracy and reduce the delay in effective way.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | system on chip (soc) electronic design automation (eda) sram (static random access memory) h-array generator network generator |
| Subjects: | Q Science > QA Mathematics > QA75 Electronic computers. Computer science QA75 Electronic computers. Computer science |
| Depositing User: | EAI Editor IV |
| Date Deposited: | 11 Jun 2021 08:01 |
| Last Modified: | 11 Jun 2021 08:01 |
| URI: | https://eprints.eudl.eu/id/eprint/3843 |
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