Design and Implementation of AGU based FFT Pipeline Architecture

Present it is most needful task to get various applications with parallel computations by using a Fast Fourier Transform (FFT) and the derived outputs should be in regular format. This can be achieved by using an advanced technique called Multipath delay commutator (MDC) Pipelining FFT processor and this processor will be capable to perform the computation of a different data streams at a time. In this paper the design and implementation of AGU based Pipelined FFT architecture is done. The proposed instructions calculate a butterfly within two cycles. The proposed architecture employs a Data Processing Unit (DPU) supporting the instructions and an FFT Address Generation Unit (FAGU) automatically calculating the butterfly input and output data addresses. The proposed DPU has a smaller area than commercial DSP chips. Moreover, the number of FFT computation cycles is reduced by the proposed FAGU. The design of FFT architecture will consists of real data paths. The FFT is mapped to pipelined architecture with different FFT sizes, different level of parallelism and various radixes. The most attractive feature of the pipelined FFT architecture is it consists of bit reversal operation so it requires little number of registers and better throughput.