FPGA Design and Optimization Implementation of GPS Positioning Algorithm

Propose a parallel data processing framework method based on field programmable gate array (FPGA). In this paper, the complexity analysis of GPS classic localization algorithm is carried out. Within the scope allowed by hardware logic resources, the FPGA hardware implementation framework is designed with the idea of area exchange rate, that is, a large number of pipeline operations are used in Verilog language programming to improve system processing speed. The experimental results show that FPGA achieves high precision positioning, in the WGS-84 coordinate system, the error of the X-axis about 5m, and the error of the Y-axis and the Z-axis is about 2m.